Routing element for use in multi-chip modules, multi-chip modules including the routing element, and methods

ABSTRACT

A routing element for use with a multi-chip module. The routing element includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a multi-chip module substrate. The conductive traces may be carried upon a single surface of the routing element substrate, internally by the routing element substrate, or include externally and internally carried portions. The routing element also includes a contact pad positioned at each end of each conductive trace thereof to facilitate electrical connection of each conductive trace to a corresponding terminal of the substrate or to a corresponding bond pad of a semiconductor device of the multi-chip module. Multi-chip modules are also disclosed, as are methods for designing the routing element and methods in which the routing element is used.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to multi-chip modules(MCMs) that include substrates with a number of semiconductor devicespositioned at different locations on the surfaces thereof and, morespecifically, to multi-chip modules that include routing elementsoverlapping portions of the multi-chip module substrate or one or moreof the semiconductor devices on the substrate. In particular, thepresent invention relates to a routing element that provides additionalcircuit traces and that may be used to decrease the lengths of circuitpaths across a multi-chip module.

[0003] 2. Background of Related Art

[0004] Multi-chip modules have been developed to combine thefunctionalities of two or more semiconductor devices on a single carriersubstrate, such as a circuit board. Conventional multi-chip modules haveincluded a relatively large carrier substrate with a number of differentsemiconductor devices occupying different regions on one or both sidesthereof. The semiconductor devices may communicate with one another orbe connected with terminals of the carrier substrate that, in turn,facilitate communication between the semiconductor devices of themulti-chip module and external electronic componentry. In either event,electrical signals are typically conveyed by circuit traces that arecarried by the carrier substrate.

[0005] As the feature densities of semiconductor devices continue toincrease, the number of bond pads on semiconductor devices may alsoincrease. In addition, the ever-increasing feature densities ofsemiconductor devices may be accompanied by decreases in the size ofsemiconductor devices which, in turn, may result in multi-chip modulesthat include increased numbers of semiconductor devices, againincreasing the number of bond pads for a particular carrier substrate.Thus, the carrier substrates of state of the art multi-chip modules mustcarry ever-increasing numbers of circuit traces to keep up with theever-increasing numbers of bond pads for which the carrier substratemust provide electrical connections.

[0006] To accommodate additional circuit traces, additional conductiveand dielectric layers are typically added to carrier substrates. Theincrease in the manufacturing cost of carrier substrates, however, doesnot increase a proportionate amount for each additional layer. Rather,while carrier substrates with four layers cost only about 50% more thantwo-layer carrier substrates, six-layer carrier substrates are about tentimes as expensive as two-layer carrier substrates due to decreasedyields. Similar cost increases accompany further increases in thecomplexity of carrier substrates. As additional layers are often addedfor the purpose of providing relatively few additional circuit traces,the increased cost of a carrier substrate with these additional layersis difficult to justify in this cost-competitive industry.

[0007] In addition, due to the ever increasing numbers of circuit tracesthat are carried upon and within multi-chip module carrier substrates,the complexities and pathlengths of the circuit traces are also everincreasing in order to minimize electrical interference between traces.

[0008] Accordingly, there appears to be a need for apparatus toaccommodate electrical connection of increasing numbers of bond padswithout requiring an increase in the number of layers and, thus, thecomplexity of a multi-chip module carrier substrate. There also appearsto be a need for apparatus that electrically connect mutually remotepads or terminals while providing the shortest possible pathlengththerebetween.

SUMMARY OF THE INVENTION

[0009] The present invention includes a routing element that isconfigured to be disposed at least partially over a substrate of amulti-chip module or semiconductor devices carried upon the substrate.The routing element includes a thin, optionally flexible, dielectricfilm that carries circuit traces. The routing element may also includecontact pads at the ends of each of the conductive traces. The routingelement and substrate collectively form a carrier for one or moresemiconductor devices of the multi-chip module.

[0010] A multi-chip module incorporating teachings of the presentinvention includes a substrate with die mounting regions on at least oneside thereof. Semiconductor devices may be positioned on correspondingdie mounting regions of the substrate. Terminals located adjacent to thedie mounting regions of the substrate communicate with correspondingconductive traces that are carried upon the substrate. Terminals locatedat opposite ends of the conductive traces are configured to facilitateelectrical connection of conductive traces and, thus, of semiconductordevice input/output pads, or bond pads, that communicate with each ofthe conductive traces to other semiconductor devices, electroniccomponents on the substrate, or components that are external to themulti-chip module.

[0011] In addition, the multi-chip module includes one or more routingelements. Routing elements may be positioned over the substrate, one ormore of the semiconductor devices on the substrate, or some combinationthereof to provide additional conductive traces through which electricalconnections may be made. Accordingly, a first terminal of the multichipmodule substrate or a first bond pad of a semiconductor device of themulti-chip module may be electrically connected to a correspondingconductive trace of a routing element which, in turn, is electricallyconnected to a corresponding second terminal of the substrate or secondbond pad of the same or a different semiconductor device, therebyestablishing communication between the first terminal or bond pad andthe second terminal or bond pad.

[0012] The path of a circuit trace of a routing element according to thepresent invention may be substantially linear and, thereby, provide ashorter conductive path length, or more direct route, from the firstterminal or bond pad to the second terminal or bond pad than would aconventional conductive trace carried by the substrate of the multi-chipmodule.

[0013] An electrical connection method employing teachings of thepresent invention includes substantially simultaneously providingconductive paths for electrical communication between a first pluralityof terminals and bond pads and corresponding terminals or bond pads of asecond plurality.

[0014] By way of example, a routing element of the present invention maybe used to simultaneously provide the conductive paths. Accordingly,such a routing element may be positioned at least partially over one orboth of a location of the substrate and a semiconductor device thereonsuch that first ends of the conductive traces of the routing elementthereon are located proximate to corresponding terminals or bond pads ofthe first plurality and second ends of the conductive traces are locatedproximate to corresponding terminals or bond pads of the secondplurality. The terminals and/or bond pads may then be electricallyconnected to their corresponding conductive traces of the routingelement.

[0015] The present invention also includes a method for designing arouting element. This method includes identifying a first plurality ofterminals or bond pads and a remote, second plurality of terminals orbond pads that are to be electrically connected to one another. Thelocations of each terminal or bond pad of the first and secondpluralities is then determined. Based on the locations of eachcorresponding pair or set of bond pads and/or terminals, the locationsof contact pads and conductive traces of a routing element may beconfigured to facilitate connection of each corresponding pair ofterminals and/or bond pads. The relative positions and orientations ofthe conductive trace locations may be configured to minimize electricalinterference between adjacent conductive traces, with any structures ofa substrate or semiconductor device that will underlie the conductivetraces, or a combination thereof. In addition, the position of eachconductive trace location, as well as the path of each conductive tracelocation, may be configured to have minimize its length while stilladdressing the foregoing concerns.

[0016] Other features and advantages of the present invention willbecome apparent to those of ordinary skill in the art throughconsideration of the ensuing description, the accompanying drawings, andthe appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In the drawings, which illustrate exemplary embodiments ofvarious aspects of the present invention:

[0018]FIG. 1 is a top view of an exemplary routing element of thepresent invention;

[0019]FIG. 2 is a cross-section taken along line 2-2 of FIG. 1;

[0020]FIG. 3 is a top view of another exemplary routing element;

[0021]FIG. 4 is a cross-section taken along line 4-4 of FIG. 3;

[0022]FIG. 5 is a top view of still another exemplary routing elementthat incorporates teachings of the present invention;

[0023]FIG. 6 is a cross-section taken along line 6-6 of FIG. 5;

[0024]FIG. 7 is a top view of an exemplary multi-chip module whichemploys two routing elements according to the present invention indifferent ways;

[0025]FIG. 8 is a top view of another multi-chip module that includes arouting element superimposed and extending over a semiconductor device;

[0026]FIG. 9 is a cross-sectional representation of yet anothermulti-chip module of the present invention, illustrating the use of anaperture to electrically connect terminals on one side of a substrate tocorresponding contact pads of a routing element on the opposite side ofthe substrate; and

[0027]FIG. 10 is a cross-sectional representation of a multi-chip modulethat includes a routing element extending from a first side of thesubstrate thereof, through an aperture, to a second side of thesubstrate thereof.

DETAILED DESCRIPTION OF THE INVENTION

[0028] With reference to FIGS. 1 and 2, an exemplary routing element 40is depicted. Routing element 40 includes a thin base base substrate 41,a plurality of conductive traces 42 carried by and extending across basesubstrate 41, and contact pads 44 located at ends of each conductivetrace 42.

[0029] Base substrate 41 of routing element 40 may be formed from adielectric material, such as a nonconductive polymer (e.g., polyimide).In addition, base substrate 41 may comprise a flexible, substantiallyplanar member, enabling base substrate 41 to conform somewhat tosurfaces that are located at different elevations (e.g., the differentelevations of a multi-chip module). Alternatively, base substrate 41 maycomprise substantially planar member formed from any other dielectricmaterial (e.g., glass, ceramic, etc.) or at least partiallydielectric-coated semiconductor material.

[0030] Each conductive trace 42, which may be formed from a lowelectrical resistance, electrically conductive material, such asaluminum or copper, extends from a location proximate a first edge 49 aof base substrate 41 to a location proximate a different, second edge 49b of substrate 41. While conductive traces 42 may be nonlinear, it ispreferred that each conductive trace 42 provide the shortest possiblepath length between a corresponding first terminal 24 a or bond pad 34 a(FIG. 7) and second terminal 24 b or bond pad 34 b (FIG. 7).Accordingly, substantially straight conductive traces 42 are within thescope of the present invention.

[0031] Conductive traces 42 are preferably positioned, oriented, andspaced on base substrate 41 relative to one another in such a manner asto reduce or eliminate any electrical interference therebetween.Conductive traces 42 of routing element 40 may be parallel ornonparallel to one another.

[0032] While conductive traces 42 may be carried on either side 43, 45of substrate 41, internally within base substrate 41, or with bothinternal and exposed portions, it is preferred that a back side 45 ofbase substrate 41 provide an electrically insulative barrier forconductive traces 42 to electrically isolate conductive traces 42 fromany conductive structures that will underlie routing element 40 uponpositioning of routing element 40 in use.

[0033] Contact pads 44 are carried upon either an upper side 43 of basesubstrate 41 at or adjacent to a peripheral edge 49 thereof or onperipheral edge 49. Such positioning of contact pads 44 facilitatesaccess thereto by equipment that will secure discrete conductiveelements 36 (FIG. 7) to contact pads 44 (e.g., a wire bonding capillary,thermocompression bonding equipment, etc.).

[0034] At least portions of back side 45 of base substrate 41 may becoated with an adhesive material 46, such as a thermoset resin or apressure-sensitive adhesive. Such a coating of adhesive material 46 mayfacilitate securing of routing element 40 to one or more other structureor structures, such as a carrier substrate, a semiconductor device, orboth. Adhesive material 46 may also electrically insulate conductivetraces 42 and contact pads 44 from underlying structures, or provide anadditional insulative layer or standoff distance that decreases oreliminates any electrical interference that may occur between underlyingstructures and conductive traces 42 or contact pads 44.

[0035] Another embodiment of routing element 140 is shown in FIGS. 3 and4. Routing element 140 includes a substrate 141 and conductive traces142 and contact pads 144 a, 144 b that are carried by substrate 141.

[0036] Contact pads 144 a are located adjacent to a first peripheraledge 149 a of substrate 141, while contact pads 144 b are locatedadjacent to a different peripheral edge 149 b of substrate 141. Inaddition, contact pads 144 a are exposed at a first side 143 ofsubstrate 141, while contact pads 144 b are exposed at an opposite side145 thereof. Contact pads 144 a, 144 b are positioned adjacent to andcommunicate with ends of each conductive trace 142.

[0037] Each conductive trace 142 includes a first portion 142 a and asecond portion 142 b. First and second portions 142 a and 142 b of eachconductive trace communicate with each other. By way of example, iffirst and second portions 142 a and 142 b are carried upon oppositesides 143, 145 of substrate 141, first and second portions 142 a and 142b of each conductive trace 142 may be electrically connected to oneanother by way of an electrically conductive via 148. One or moreregions along the lengths of first and second portions 142 a and 142 bmay be coated with a dielectric material 147 to electrically insulatethese portions from any structures that may contact the same in use.

[0038] Another exemplary embodiment of routing element 140′incorporating teachings of the present invention is depicted in FIGS. 5and 6. Rereouting element 140′ includes a substrate 141′, as well asconductive traces 142′ and contact pads 144 a′ and 144 b′ that arecarried by substrate 141′.

[0039] At least a portion of the length of each conductive trace 142′ ofrouting element 140′ is carried internally within substrate 141′.Therefore, substrate 141′ substantially electrically insulates theinternalized portion of each conductive trace 142′. Contact pads 144 a′and 144 b′ facilitate communication with conductive traces 142′. A firstcontact pad 144 a′is positioned at a first end of each conductive trace142′, while a second contact pad 144 b′is located at a second end ofeach conductive trace 142′. Contact pads 144 a′ are located adjacent toa different peripheral edge 149 a′ of substrate 141′ than the peripheraledge 149 b′ near which contact pads 144 b′ are located. In addition,contact pads 144 a′ and 144 b′ are positioned on opposite sides 143′,145′ of substrate 141′.

[0040] In designing a routing element according to the presentinvention, several factors may be considered. For example, the locationsof each of the terminals or bond pads of a multi-chip module betweenwhich a conductive trace of the routing element is to provide aconductive path may be considered. In addition, the shapes, locations,orientations, and positions of the conductive traces may be configuredto minimize the lengths thereof, to reduce or eliminate the potentialfor interference between the conductive traces of the routing element orbetween the conductive traces and features that are external to therouting element, or a combination thereof. Further, the manner in whichthe conductive traces or portions thereof are carried by the substrate(i.e., internally or externally) may be configured based on the types ofstructures that will, in use of the designed routing element, be locatedadjacent thereto. The routing element may also be configured to includeinsulative coatings on portions or all of the conductive traces thereof.Contact pads of a routing element may be configured based on the type ofelectrical connection that will be used therewith (e.g., wire bonding,tape-automated bond (TAB) elements carried by a polymeric film,thermocompression bonded leads, use of solder balls, etc.).

[0041] Turning now to FIG. 7, an exemplary embodiment of a multi-chipmodule 10 is illustrated. Multi-chip module 10 includes a MCM substrate20, which is also referred to herein as a carrier substrate, andsemiconductor devices 30 that are secured to MCM substrate 20. As usedherein, the term “semiconductor device” includes, without limitation,semiconductor dice, as well as full or partial wafers or otherlarge-scale semiconductor substrates upon which a number ofsemiconductor dice fabricated thereon. Routing elements 40 may bepositioned over portions of one or both of MCM substrate 20 andsemiconductor devices 30. In addition, multi-chip module 10 may includeone or more passive devices, such as capacitors, resistors, batteries,indicators, and the like. These passive devices may be electricallyconnected to MCM substrate 20 and/or one or more semiconductor devices30 by way of conductive traces carried by MCM substrate 20, routingelements 40, or a combination thereof.

[0042] Multi-chip module 10 may also include one or more externalconnective elements 50, which facilitate communication betweensemiconductor devices 30 or other electronic components of multi-chipmodule 10 and componentry, such as a motherboard or other higher levelpackaging, external to multi-chip module 10. Although externalconnective elements 50 are depicted as plug-in type edge connectors,other types of external connective elements are also within the scope ofthe present invention, including, without limitation, balls, bumps,pillars, and columns, of electrically conductive material (e.g., solder,other metals, conductive epoxy, conductor-filled epoxy, z-axisconductive elastomer, etc.), as well as conductive pins.

[0043] MCM substrate 20 may comprise a circuit board or any other typeof substrate that may be used in multi-chip modules. By way of exampleonly, a circuit board that includes two or four wiring layers, may beused as MCM substrate 20. MCM substrate 20 includes die attach locations26 on at least one side thereof. MCM substrate 20 also carriesconductive traces (not shown) and their corresponding terminals 24, aswell as terminals 24 that do not correspond to any conductive traces.

[0044] Conductive traces may extend across one or more layers of MCMsubstrate 20, as well as vertically through MCM substrate 20, betweendifferent wiring layers thereof. Each conductive trace facilitates thecommunication of electrical signals between at least first and secondlocations of MCM substrate 20, such as die attach regions 26 thereof,which locations correspond to the two ends of each conductive trace. Atleast one of the first and second locations between which eachconductive trace extends may be positioned proximate a die attach region26 of MCM substrate 20.

[0045] A terminal 24 is located at each end of each conductive trace.Terminals 24 facilitate the electrical connection of each conductivetrace to another, corresponding terminal 24 carried by MCM substrate 20or to a corresponding bond pad 34 of a semiconductor device 30 on MCMsubstrate 20.

[0046] Each semiconductor device 30 may be secured to a correspondingdie attach region 26 of MCM substrate 20. Discrete conductive elements36, such as bond wires, TAB elements, thermocompression bonded leads, orthe like, may electrically connect and, thus, establish communicationbetween bond pads 34 of each semiconductor device and theircorresponding terminals 24 and, thus, corresponding conductive tracescarried by MCM substrate 20. Both bond pads 34 and terminals 24 are alsoreferred to herein as contact areas.

[0047] Alternatively, discrete conductive elements 36 may connect bondpads 34 of semiconductor devices 30 or terminals 24 of MCM substrate 20to corresponding contact pads 44 of a routing element 40 positionedadjacent thereto. The connected bond pads 34 or terminals 24 may thencommunicate with corresponding, remote bond pads 34 or terminals 24 byway of conductive traces 42 of routing element 40.

[0048] As depicted in FIG. 7, as a first example of the placement anduse of a routing element 40 in multi-chip module, a routing element 40 amay be positioned over a region of MCM substrate 20 that is locatedbetween two semiconductor devices 30 a and 30 b. Bond pads 34 a ofsemiconductor device 30 a may be electrically connected to, orcommunicate with, corresponding terminals 24 a of MCM substrate 20 byway of discrete conductive elements 36. discrete conductive elements 36may also electrically connect, or establish communication between,terminals 24 a and corresponding contact pads 44 a of routing element 40a. Each contact pad 44 a of routing element 40 extends substantiallyacross base substrate 41 thereof to another contact pad 44 b locatedproximate an opposite edge 49 b of base substrate 41 from itscorresponding contact pad 44 a. Contact pads 44 b are also electricallyconnected to, or communicate with, corresponding terminals 24 b by wayof discrete conductive elements 36. Additional discrete conductiveelements 36 are positioned between each terminal 24 b of MCM substrate20 and a corresponding bond pad 34 b of semiconductor device 30 b. Thisseries of discrete conductive elements 36 and conductive traces 42establishes electrical communication between each first bond pad 34 aand its corresponding second bond pad 34 b.

[0049]FIG. 8 depicts an alternative embodiment of multi-chip module 10′,which includes a MCM substrate 20′, semiconductor devices 30 a, 30 b,and a routing element 40 that are similar to those described herein withreference to FIG. 7. In addition, multi-chip module 10′ includes anothersemiconductor device 30 c. Discrete conductive elements 36 electricallyconnect bond pads 34 c of semiconductor device 30 c to correspondingterminals 24 c of MCM substrate 20′.

[0050] Again, discrete conductive elements 36 and features of routingelement 40 electrically connect bond pads 34 a of semiconductor device30 a to corresponding bond pads 34 b of semiconductor device 30 b.Rather than extend only over a portion of MCM substrate 20′, however,routing element 40 is also superimposed over semiconductor device 30 andover at least some discrete conductive elements 36 that electricallyconnected bond pads 34 c thereof to their corresponding terminals 24 c.

[0051] With reference again to FIG. 7, another example of the placementand use of a routing element 40″ in multi-chip module 10 is depicted. Inthis example, an entire routing element 40″ may be positioned over aportion of a semiconductor device 30″. Bond pads 34 a″-34 d″ ofsemiconductor device 30″ are exposed beyond an outer periphery 49″(which includes edges 49 a″-49 d″) of a base substrate 41″ of routingelement 40″. As depicted, routing element 40″ is used to electricallyconnect and establish communication between bond pads 34 a″ positionedproximate a first edge 39 a″ of semiconductor device 30″ andcorresponding terminals 24 a″ located adjacent another edge 39 c″ ofsemiconductor device 30″. Discrete conductive elements 36 electricallyconnect a bond pad 34 a″ to an adjacently positioned, correspondingcontact pad 44 a″ of routing element 40″. Likewise, a correspondingcontact pad 44 c″, located at an opposite end of conductive trace 42″from contact pad 44 a″, may be electrically connected to a correspondingterminal 24 c″ by way of a discrete conductive element 36.

[0052] Remaining bond pads 34 a″-34 d″ of semiconductor device 30″ mayalso be electrically connected to adjacent, corresponding terminals 24a-24 d of MCM substrate 20 by way of discrete conductive elements 36that extend from bond pads 34 a″-34 d″, over edges 39 a″-39 d″, toterminals 24 a-24 d. Terminals 24 a-24 d, in turn, facilitatecommunication with semiconductor devices or other electronic componentslocated elsewhere on MCM substrate 20, or with componentry that isexternal to multi-chip module 10.

[0053] Referring now to FIG. 9, another embodiment of multi-chip module10″ is depicted. MCM substrate 20″ of multi-chip module 10″ includes atleast one aperture 28″ formed therethrough. Aperture 28″ is locatedadjacent to one or both of a group of terminals 24 a and a die mountinglocation 26″ on a first side 23″ of MCM substrate 20″.

[0054] A routing element 140, 140′ is positioned on an opposite, secondside 25″ of MCM substrate 20″ so as to overlap at least a portion ofaperture 28″, with a first group of contact pads 144 a, 144 a′ thereofbeing exposed through aperture 28″. A second group of contact pads 144b, 144 b′ of routing element 140, 140′ are positioned proximate tocorresponding terminals 24 b of MCM substrate 20″ and/or bond pads 34 bof a semiconductor device 30 (FIG. 7) on second side 25″ of MCMsubstrate 20″. Discrete conductive elements 36 extend through aperture28″, or otherwise through a plane of MCM substrate 20″, to electricallyconnect terminals 24 a on first side 23″ to contact pads 144 a, 144 a′.Contact pads 144 b, 144 b′ are also electrically connected tocorresponding terminals 24 b or bond pads 34 b (FIG. 7) on second side25″ by way of discrete conductive elements 36.

[0055] The multi-chip module 10′″ shown in FIG. 10 includes a MCMsubstrate 20′″ with an aperture 28′″ formed therethrough at anintermediate location between a first group of terminals 24 a or a firstdie attach region 26 a′″ on a first side 23″′ thereof and a second groupof terminals 24 b or a second die attach region 26 b′″ on an opposite,second side 25″′ thereof.

[0056] A routing element 140, 140′ extends through aperture 28′″, with afirst group of contact pads 144 a thereof being positioned proximate toone or both of terminals 24 a of the first group and bond pads of asemiconductor device secured to die attach region 26 a. A second groupof contact pads 144 b, which are located at an opposite end of routingelement 140, 140′, are positioned proximate to one or both of terminals24 b or the second group and bond pads of a semiconductor device securedto die attach region 26 b′″. While connections between contact pads 144a, 144 a′, 144 b, 144 b′ and their respective, corresponding terminals24 a, 24 b or bond pads (not shown) are depicted as being made by way ofdiscrete conductive elements 36 in the form of wire bonds, other typesof discrete conductive elements 36, including, without limitation, TABelements and thermocompression bonded leads, may be used to electricallyconnect contact pads 144 a, 144 b to terminals 24 a, 24 b or bond pads(not shown) that are facing in the same general direction.

[0057] Alternatively, contact pads 44 a, 44 b, 144 a, 144ab of anyrouting element (e.g., routing elements 40, 40′, 40″, 140, 140′)incorporating teachings of the present invention may be positioned ontop of their corresponding terminals 24 a, 24 b or bond pads (not shown)to facilitate bonding thereto by way of discrete conductive elementssuch as thermocompression bonded leads, solder balls, or the like.

[0058] Although the foregoing description contains many specifics, theseshould not be construed as limiting the scope of the present invention,but merely as providing illustrations of some exemplary embodiments.Similarly, other embodiments of the invention may be devised which donot depart from the spirit or scope of the present invention. Featuresfrom different embodiments may be employed in combination. The scope ofthe invention is, therefore, indicated and limited only by the appendedclaims and their legal equivalents, rather than by the foregoingdescription. All additions, deletions, and modifications to theinvention, as disclosed herein, which fall within the meaning and scopeof the claims are to be embraced thereby.

What is claimed is:
 1. A routing element for use in a semiconductordevice assembly, comprising: a polymeric film; and at least oneconductive trace including first and second portions carried adjacentopposite sides of said polymeric film, said at least one conductivetrace located so as to facilitate electrical connection between remotefirst and second locations of the semiconductor device assembly.
 2. Therouting element of claim 1, further comprising: a contact pad located ateach end of said at least one conductive trace.
 3. The routing elementof claim 2, wherein said contacts are located on opposite sides of saidpolymeric film from one another.
 4. The routing element of claim 1,wherein said polymeric film is substantially planar.
 5. The routingelement of claim 1, wherein said polymeric film is flexible.
 6. Therouting element of claim 1, wherein said at least one conductive traceextends from a first location proximate a first edge of said polymericfilm to a second location proximate an opposite, second edge of saidpolymeric film.
 7. The routing element of claim 1, wherein saidpolymeric film carries a plurality of conductive traces.
 8. The routingelement of claim 1, wherein at least a portion of said at least oneconductive trace is carried internally within said polymeric film. 9.The routing element of claim 1, wherein an electrically conductive viathat extends at least partially through said polymeric film electricallyconnects said first and second portions.
 10. A semiconductor deviceassembly comprising: a substrate; at least one semiconductor devicesecured to said substrate; and a polymeric film positioned at leastpartially over at least one of said substrate and said at least onesemiconductor device, said polymeric film carrying at least oneconductive trace in communication with at least one of a terminal ofsaid substrate and a bond pad of said at least one semiconductor device.11. The assembly of claim 10, wherein said polymeric film is at leastpartially superimposed over said at least one semiconductor device. 12.The assembly of claim 11, wherein said at least one conductive trace atleast partially establishes communication between a bond pad of said atleast one semiconductor device and a corresponding terminal of saidsubstrate.
 13. The assembly of claim 12, wherein communication betweensaid bond pad and said corresponding terminal is further established byat least one discrete conductive element positioned electrically betweensaid at least one conductive trace and at least one of said bond pad andsaid corresponding terminal.
 14. The assembly of claim 10, comprising aplurality of semiconductor devices at different locations on saidsubstrate.
 15. The assembly of claim 14, wherein said polymeric film issecured to said substrate laterally between at least two semiconductordevices of said plurality of semiconductor devices.
 16. The assembly ofclaim 15, wherein at least one conductive trace of said plurality ofconductive traces carried by said polymeric film at least partiallyestablishes communication between a bond pad of one of said at least twosemiconductor devices and a corresponding bond pad of another of said atleast two semiconductor devices.
 17. The assembly of claim 16, whereinsaid at least one conductive trace communicates with a terminal of saidsubstrate which, in turn, communicates with said bond pad.
 18. Theassembly of claim 17, further comprising discrete conductive elementsbetween said terminal and each of said at least one conductive trace andsaid bond pad.
 19. The assembly of claim 10, wherein said substratecomprises at most four conductive layers.
 20. The assembly of claim 10,wherein said plurality of conductive traces of said polymeric filmprovide a more direct electrical route between than any conductive tracecarried by said substrate.
 21. The assembly of claim 16, wherein anotherbond pad of said one semiconductor device is in communication with atleast a terminal of said substrate by way of another conductive tracecarried by said polymeric film.
 22. The assembly of claim 10, whereinsaid polymeric film and said at least one conductive trace extendthrough a plane of said substrate.
 23. The assembly of claim 22, whereinopposite ends of said at least one conductive trace are electricallyexposed at opposite sides of said polymeric film.
 24. The assembly ofclaim 22, wherein opposite ends of said at least one conductive traceare electrically exposed at the same side of said polymeric film.
 25. Acarrier for at least one semiconductor device, comprising: a substratecarrying at least one terminal and at least one conductive trace; and apolymeric film positioned at least partially over said substrate andcarrying at least one additional conductive trace.
 26. The carrier ofclaim 25, wherein said substrate comprises at most four conductivelayers.
 27. The carrier of claim 25, wherein said polymeric film is atleast partially adhered to said substrate.
 28. The carrier of claim 27,wherein said at least one additional conductive trace at least partiallyestablishes communication between said at least one terminal and anotherterminal carried upon said substrate.
 29. The carrier of claim 28,wherein communication between said at least one terminal and saidanother terminals is further established by way of at least one discreteconductive element that electrically connects said at least oneadditional conductive trace to at least one of said at least oneterminal and said another terminal.
 30. The carrier of claim 25, whereinsaid polymeric film is configured to be disposed at least partially overthe at least one semiconductor device carried by said substrate.
 31. Thecarrier of claim 25, wherein said at least one additional conductivetrace carried upon said polymeric film is configured to at leastpartially establish communication between said at least one terminal anda corresponding bond pad of the at least one semiconductor device. 32.The carrier of claim 31, wherein communication between said at least oneterminal and said corresponding bond pad is further established by wayof at least one discrete conductive element electrically connecting saidat least one additional conductive trace to at least one of said atleast one terminal and said corresponding bond pad.
 33. The carrier ofclaim 31, wherein said at least one additional conductive trace carriedupon said polymeric film is configured to at least partially establishcommunication between a bond pad of the at least one semiconductordevice and a corresponding bond pad of at least another semiconductordevice carried by said substrate.
 34. The carrier of claim 33, whereincommunication between said bond pad and said corresponding bond pad isfurther established by way of at least one discrete conductive elementelectrically connecting said at least one additional conductive traceand at least one of said bond pad and said corresponding bond pad. 35.The carrier of claim 25, wherein said substrate includes at least oneaperture formed therethrough for receiving a portion of said polymericfilm and said at least one additional conductive trace to facilitatepositioning of different portions of said polymeric film over portionsof opposite sides of said substrate.
 36. The carrier of claim 35,wherein opposite ends of said at least one additional conductive traceare electrically exposed at opposite sides of said polymeric film. 37.The carrier of claim 35, wherein opposite ends of said at least oneadditional conductive trace are electrically exposed at the same side ofsaid polymeric film.
 38. A method for designing a routing element foruse in a semiconductor device assembly, comprising: configuring apolymeric film to be disposed between at least two areas of at least oneof a substrate and a semiconductor device; and configuring at least oneconductive trace to be carried by said polymeric film and to extendsubstantially between locations of said polymeric film adjacent to saidat least two areas upon said disposition of said polymeric film.
 39. Themethod of claim 38, wherein said configuring said polymeric filmcomprises configuring said polymeric film to electrically insulate atleast portions of said at least one conductive trace.
 40. The method ofclaim 38, wherein said configuring said at least one conductive tracecomprises configuring said at least one conductive trace to be at leastpartially carried internally within said polymeric film.
 41. The methodof claim 38, wherein said configuring said at least one conductive tracecomprises configuring said at least one conductive trace to extendsubstantially between a first contact area and a second contact area.42. The method of claim 38, wherein said configuring said at least oneconductive trace comprises configuring a plurality of conductive traces.43. The method of claim 42, wherein said configuring said plurality ofconductive traces comprises configuring positions of each of saidplurality of conductive traces so as to minimize electrical interferencebetween conductive traces of said plurality.
 44. The method of claim 38,wherein said configuring said at least one conductive trace comprisesconfiguring a position of said at least one conductive trace to extendsubstantially directly between said at least two areas.
 45. A method forestablishing electrical connections in a semiconductor device,comprising: providing a substrate including at least one first contactarea and at least one remote, unconnected, corresponding second contactarea; positioning at least one routing element carrying at least oneconductive trace between said at least one first contact area and saidat least one second area with ends of said at least one conductive traceextending proximate said at least one first contact area and said atleast one second contact area; and electrically connecting said at leastone conductive trace between said at least one first contact area andsaid at least one second contact area.
 46. The method of claim 45,wherein said providing comprises providing at least one semiconductordevice on said substrate, said at least one semiconductor devicecomprising at least one of said at least one first contact area and saidat least one second contact area.
 47. The method of claim 46, whereinsaid positioning comprises positioning said at least one routing elementat least partially over said at least one semiconductor device.
 48. Themethod of claim 46, wherein said positioning comprises positioning saidat least one routing element laterally adjacent to said at least onesemiconductor device.
 49. The method of claim 45, wherein saidpositioning comprises positioning said at least one routing elementadjacent to conductive traces carried by said substrate with said atleast one conductive trace of said at least one routing elementelectrically isolated from said conductive traces carried by saidsubstrate.
 50. The method of claim 45, wherein said electricallyconnecting comprises electrically connecting comprises disposing adiscrete conductive element between said at least one conductive traceand each of said at least one first contact area and said at least onesecond contact area.
 51. The method of claim 45, wherein saidpositioning comprises extending a portion of said at least one reroutingelement through a plane of said substrate to locate a first end of saidat least one conductive trace proximate said at least one first contactarea and a second end of said at least one conductive trace proximatesaid at least one second contact area, located on an opposite side ofsaid substrate from said at least one first contact area.
 52. A methodfor designing a carrier, comprising: configuring a substrate;configuring at least one region on said substrate to receive asemiconductor device; configuring a first plurality of conductive tracesto be carried by said substrate; and configuring at least one routingelement to carry a second plurality of conductive traces, said routingelement to be assembled with said substrate.
 53. The method of claim 52,further comprising configuring terminal pads on at least one surface ofsaid substrate.
 54. The method of claim 53, wherein said configuringterminals pads comprises configuring a first plurality of terminal padsto electrically communicate with said first plurality of conductivetraces.
 55. The method of claim 54, wherein said configuring terminalpads further comprises configuring a second plurality of terminal padsto electrically communicate with said second plurality of conductivetraces upon assembly of said at least one routing element with saidsubstrate.
 56. The method of claim 52, wherein said configuring saidfirst plurality of conductive traces comprises configuring said firstplurality of conductive traces to extend along at most four conductivelayers of said substrate.
 57. The method of claim 52 wherein saidconfiguring said at least one routing element comprises configuring saidsecond plurality of conductive traces to extend to a location proximatesaid at least one region upon assembly of said at least one routingelement with said substrate.
 58. The method of claim 52, furthercomprising configuring an aperture through said substrate.
 59. Asemiconductor device assembly comprising: a substrate carrying a firstplurality of conductive traces; a routing element carrying a secondplurality of conductive traces positioned at least partially on saidsubstrate; and at least one semiconductor device secured to saidsubstrate.
 60. The assembly of claim 59, wherein said routing element isat least partially superimposed over said at least one semiconductordevice.
 61. The assembly of claim 60, wherein at least one conductivetrace of said second plurality of conductive traces at least partiallyestablishes electrical communication between a bond pad of said at leastone semiconductor device and a corresponding terminal of said substrate.62. The assembly of claim 61, wherein communication between said bondpad and said corresponding terminal is further established by at leastone discrete conductive element positioned electrically between said atleast one conductive trace and at least one of said bond pad and saidcorresponding terminal.
 63. The assembly of claim 59, comprising aplurality of semiconductor devices at different locations on saidsubstrate.
 64. The assembly of claim 63, wherein said routing element issecured to said substrate laterally between at least two semiconductordevices of said plurality of semiconductor devices.
 65. The assembly ofclaim 64, wherein at least one conductive trace of said second pluralityof conductive traces at least partially establishes communicationbetween a bond pad of one of said at least two semiconductor devices anda corresponding bond pad of another of said at least two semiconductordevices.
 66. The assembly of claim 65, wherein said at least oneconductive trace communicates with a terminal of said substrate which,in turn, communicates with said bond pad.
 67. The assembly of claim 66,further comprising discrete conductive elements between said terminaland each of said at least one conductive trace and said bond pad. 68.The assembly of claim 59, wherein said substrate comprises at most fourconductive layers.
 69. The assembly of claim 58, wherein said pluralityof conductive traces of said routing element provide a more directelectrical route between than any conductive trace carried by saidsubstrate.
 70. The assembly of claim 65, wherein another bond pad ofsaid one semiconductor device is in communication with at least aterminal of said substrate by way of another conductive trace of saidsecond plurality of conductive traces.
 71. The assembly of claim 59,wherein said routing element and said at least one conductive traceextend through a plane of said substrate.
 72. The assembly of claim 71,wherein opposite ends of said at least one conductive trace areelectrically exposed at opposite sides of said routing element.
 73. Theassembly of claim 71, wherein opposite ends of said at least oneconductive trace are electrically exposed at the same side of saidrouting element.